Printed Wiring Board (PWB) technology relies primarily upon copper-plated, drilled holes known as "through holes" to make connections from one surface of the board to the other. The most common configuration of a PWB consists of a glass weave reinforced epoxy, polyester or phenolic resin core, sheets of copper that have been laminated to either surface of the core and selectively etched into circuit patterns, and mechanically drilled through-holes with diameters on the order of 8 mil to 30 mil that have been subsequently plated with copper to connect to the circuitry on either side. In more sophisticated PWB's, there is often a need for additional layers of circuitry to make all of the necessary interconnections. In this case, a multiplicity of core substrates with circuitry on both sides are interleaved with unmetalized electrically insulating cores and laminated together into a monolithic structure. This structure is subsequently mechanically drilled through the entire thickness of the stack, and copper is plated into the holes to form interconnections between layers of circuitry.
This type of multilayered printed wiring board construction necessitates large "capture" features to be incorporated into circuit layers so that misplacement of the drill bit and/or misalignment of the layers, within reasonable tolerances, will not result in missed connections and unacceptable yield losses. These capture pads take up considerable area on each circuit layer resulting in significant loss of available space for additional circuitry or component attachment sites. There is additional loss of available space for circuitry on the innerlayers since, although not all circuit layers require interconnection at every drilled vertically interconnected assembly (via) location, the holes must extend through the entire thickness of the stack. Some of the lost area can be recovered by the use of smaller drill bit sizes, however, mechanical drilling becomes cost prohibitive below 8mil diameter holes due to bit breakage.
The incentive to develop improved PWB technologies has increased dramatically in the last decade for two primary reasons: First, the number of components and the number of output sites for each component has increased dramatically, resulting in orders of magnitude more attachment points per area of printed wiring board. Second, there is a drive to reduce the cost of packaged integrated circuits by building such packages using PWB technology instead of ceramic technology. Both of these factors create a need for PWB technology with higher circuit density.
A number of technologies are under development to address the increased circuit density requirements. Several of these methods rely upon the use of direct layer-to-layer interconnections instead of creating vertical electrical interconnection by drilling through the entire stack. In most of these methods, thin layers of a polymeric dielectric material replace thick cores in multilayer constructions. Vias are created by forming holes in individual layers of dielectric, either as a freestanding layer, or after the layer has been applied to previous layers. The vias thus formed are either coated or filled with a conductive medium such as copper or silver-filled epoxy, thus creating a conductive "microvia." The defining characteristic of a microvia is that it serves to connect two circuit layers in immediate proximity to one another, and no others, and that it has a diameter of less than 10 mil.
Coated microvias result in a dimple type topology whereas filled microvias form a solid plug that is co-planar with the upper conductive surface. Filled microvias are advantageous because they do not cause deformations in overlying circuit layers, they form more robust connections, and they can be stacked directly on top of one another from one circuit layer to the next, thus resulting in higher overall density capabilities and shorter circuit pathways. The problem with most of these filled via technologies is that they employ metal particulate-filled polymers as the conductive via fill material. These materials are deficient in that they do not typically share the expansion characteristics of the core substrates or inner layer dielectric, they tend to have entrapped voids when deposited into deep holes, and they suffer from loss of electrical conductivity in hot and/or humid conditions due to loss of contact between the particulates. Even when conduction pathways remain intact, they are inferior to those provided by pure metal conductors.
The use of microvias in thin dielectrics to form multilayer PWBs has resulted in very high density electronic modules with average feature sizes that are five times smaller than were typical only a few years ago. In fact, the feature sizes have decreased to the point that surface topography created by the glass-weave reinforcement in the core substrate is beginning to distort feature definition and signal propagation characteristics. Planarization of the core substrate and each intermediate layer is becoming critical for cutting edge, high density applications. The use of area array component attachment technology also acts as a driver for overall planar modules since the solder balls used to connect such devices are inherently less forgiving to surface topography than conventional metal leads. Elimination of the thick core board might seem a solution to this dilemma, however, often a thick substrate is required to provide adequate mechanical strength and dimensional control to the entire PWB structure.
In addition to planarity and density concerns, heat has become an issue for high density PWBs from two perspectives. From an external perspective, portable electronics and increasingly electronically-driven transportation systems require electronic modules to perform reliably in much more demanding environmental conditions. These operating conditions have necessitated the development of more stringent reliability assessment tests than have typically been administered. Electronic modules and subsystems are now routinely tested to 150.degree. C. instead of the previous standard of 125.degree. C.
The increased 150.degree. C. temperature for thermal cycling and shock requirements is far in excess of the glass transition temperatures of most resins used in the manufacture of core substrates. Polymer resins expand roughly linearly with temperature until their glass transition temperatures, after which, the rate of increase of expansion generally increases several fold. The expansion of the polymer resins used in core substrates during thermal excursions is mitigated in the plane of the circuit traces by the influence of the woven reinforcement material, typically glass, which has a low and stable expansion. In the axis perpendicular to the circuit layers, however, the plies of woven reinforcement are not interconnected and the resin is free to expand to its full extent. This expansion creates a considerable amount of stress on the through holes or vias in the core substrate since the conductive material possesses different expansion characteristics than the core resin. Eventually, with repeated thermal cycling, the conductive material within the vias separates from the planar circuit layers resulting in catastrophic failure.
The second heat issue is internally generated heat. Devices are packed so closely together on high-density PWBs that there is insufficient airflow to convectively carry away waste heat generated by the working devices. This problem is exacerbated by the new, more powerful IC devices, since every generation creates higher wattages over smaller effective areas. Heat sinks and active cooling devices often have to be connected to the module, and in some cases even the device, in order to effectively dissipate the heat generated so that it does not affect the module performance and life span. These cooling mechanisms are expensive, bulky, and have a detrimental effect on overall yield in manufacture.
In order to address the planarity, dimensional stability and thermal management concerns, several technology developers have turned to insulated metal substrates as core materials. Depending on the thermal dissipation requirements, substrates such as copper, aluminum, or metal matrix composites can be employed. Specific materials may be chosen based upon having expansion characteristics that match some other element in the electronic module that is of particular concern in fatigue resistance, for instance, an IC device that is directly attached to the substrate by solder balls in a "flip chip" arrangement.
Typically, the thermally and electrically conductive core materials are electrically insulated using a polymer resin that has been filled with a thermally conductive particulate material or using an inorganic coating such as glass or ceramic. Use of a conductive substrate provides some additional benefits such as high transition temperatures for changes in dimensional characteristics, less absorption of contaminate materials and inherently included power or ground planes.
Metal core substrate technology has not been widely adopted, despite its many advantages, because there is currently no accepted technique for creating insulated metal features through the thickness of the core. This deficiency necessitates that all circuitry be built on one side of the substrate. These deficiencies result in lower overall circuit density, and significant stress and camber issues if a larger number of layers of circuitry are required.
Thus, there exists a need in the industry for a technology that can utilize metal and metal matrix composite substrates in the manufacture of high density, multilayer electronic packaging. In order to satisfy industry requirements and provide significant market advantage such a technology must be simple, rugged, high-yield, cost effective, able to leverage existing PWB infrastructure, be compatible with multilayering technologies already under development, be capable of providing small through-vias and be able to utilize both surfaces of the substrate.